For the fabrication of integrated circuits the technological challenges of patterned metallization have continually increased as device dimensions have progressed into the sub micron regime. For integrated circuit needs, in general, metallization requirements have continued to be that of low bulk resistivity, high resistance to electromigration and high resistance to corrosion and oxidation, to name a few. Aluminum and its alloys have long been the materials of choice for meeting such requirements. However, as device dimensions have further progressed down into the deep sub micron regime, aluminum has started to become a serious limitation for circuit speed and copper, Cu, has emerged as its likely successor. This is due to the undesirable trend of metallization interconnects becoming a very significant contributor to signal delays on a chip, in comparison to inherent device delays. These interconnect related signal delays are associated with the line resistance, R, of the interconnect, along with the distributed capacitance, C, between the interconnect lines and signal ground. Relatively high values of R tend to limit the rate of electrical charging of C, in order for signals to rapidly propagate from one device to another. Hence, such undesirable delays increase with an increasing RC product. Unfortunately, as device dimensions have continued to shrink, efforts to maintain a sufficiently minimized RC product have encountered serious materials limitations. Consequently, new materials, such as copper interconnects and low dielectric constant (k) inter level insulators are being developed for near term and future products. If one could simply change from aluminum (bulk resistivity=2.65 uohm-cm) to copper (bulk resistivity=1.67 uohm-cm), the value of R would be reduced by about 37%. Similarly, for inter level insulators, changing from a common present day material, TEOS (k=4.2), to a recent experimental material, such as xerogel (k=1.3-3.0), substantial reductions in the value of C would also be expected.
The search for a generally acceptable inter level insulator material, with a sufficiently low value of k, is still open to investigation. In contrast, the search for an inter level metal material, with a sufficiently low value of bulk resistivity, has already narrowed down to copper, mainly. Copper is also superior to aluminum, in terms of higher resistance to electromigration. However, copper has its own particular problems. In contrast to aluminum, some of the problems with copper are: (1) The ability to rapidly diffuse into silicon device regions and behave as a highly detrimental generation-recombination center, (2) poor adhesion to insulator surfaces, and (3) the inability to produce a self passivating oxide film that will minimize corrosion and further oxidation. Considerable development efforts in the semiconductor industry have already taken place for minimizing such problems. The general approach has been to encapsulate the copper lines with one or more of a group of materials that tend to self passivate while also acting as a diffusion barrier to copper. Such self passivating barrier materials, frequently mentioned in outside publications, are: Titanium Nitride, TIN, and other refractory metals such as Tantalum, Ta,
Molybdenum, Mo, Niobium, Nb and Chromium, Cr.
U.S. Pat. No. 5,277,985, to Li, et. al., teaches a method for encapsulating copper interconnect lines with a TiN film. The method exploits the alloying of copper with titanium as a means of eventually forming a Titanium rich film on the surface of a patterned copper interconnect, after a rapid thermal heat treatment. Following a lift off process to pattern the copper interconnect layer, the titanium surface film is subsequently converted to TiN by a relatively low temperature heat treatment in an ammonia atmosphere. Although, perhaps, lending itself to the passivation of copper lines after a dry etch, once an alloy is formed between Cu and Ti, the resultant consumption of Cu will result in higher undesirable contact resistance.
U.S. Pat. No. 5,705,857, to Farooq et. al., teaches a method for encapsulating copper interconnect lines using protective barrier layers, such as Ti, Cobalt, Co, and Cr. The copper is first selectively plated through a patterned photoresist layer and onto a combined seed layer (such as a thin film of copper) and barrier layer (such as titanium). A subsequent heat treatment causes the photoresist to pull back and expose the side walls of the resultant patterned copper layer, whose top surface and side walls are then capped off by a final barrier material such as Nickel, Ni. This method has been developed for a plating based process and the associated thermal pull back of the photoresist layer seems difficult to control, during manufacturing, for addressing side wall passivation after a dry etch process.
U.S. Pat. No. 5,744,394, to Iguchi, et. al., teaches a series of damascene process steps for forming patterned copper interconnects with barrier layers composed of Ti, or Ta or Tungsten, W containing compounds. U.S. Pat. No. 5,595,937, to Mikagi, also teaches a series of damascene process steps for forming patterned copper interconnects with the added feature of a seamless interface to underlying copper contact plugs. In one preferred embodiment, a thin laminate of TiN/Ti is used as the barrier material. In addition an underlying silicon nitride spacer is employed as part of the overall barrier layer for the subsequently formed copper contact plugs. The passivation methods employed in these damascene based methods are dependent on the presence of a barrier material on buried copper sidewalls prior to copper patterning (with Chemical Mechanical Polishing, CMP) and are, therefore, only suitable for a damascene process.